The present invention relates to the speech path switch for a time divisional telephone switching system, in particular, relates to the speech path switch which provides the full availability switching, having the function of the combined highway space switch and memory switch, between nk number of input circuits in which each of k number of incoming highways has n number of time divisioned circuits, and nk number of similar outgoing circuits.
The switching system having the function of the combined highway space switch and memory switch is called a "C" switch.
A prior C switch is shown in FIG. 1. In the figure, the reference numeral 1 is a speech path memory, 2 is a speech holding memory having nk words for nk speech paths. The reference numeral 3 is a counter the content of which changes cyclicly from zero to nk-1. The counter 3 is incremented by an input clock pulse having the period 1/(nk) wherein the time unit is the time-divisional multiplex frame period. The reference numeral 4 is a multiplexing circuit for multiplexing the incoming highway 6-1, 6-2, . . . 6-k to a single secondary highway 8, and 5 is a demultiplexing circuit for demultiplexing the single secondary output highway 9 to k number of outgoing highway 7-1, 7-2, . . . 7-k. The operation of the counter 3 is synchronized with the multiplexed frames on the secondary incoming highway 8, and when the i'th speech is on the secondary highway 8, the content of the counter 3 is (i). The information of the i'th speech path on the secondary highway 8 is stored in the address (i) of the speech path memory 1. Said address (i) of the memory 1 is provided from the counter 3. At the same time, said address (i) of the counter 3 is applied to the speech holding memory 2, and the information (j) in the address (i) of said speech holding memory 2 is read out. Said information (j) is applied to the speech path memory 1 as the address information to read out the address (j), the content of which is transmitted to an external circuit as the i'th speech path information on the secondary outgoing highway 9.
Similarly, the holding memory 2 has the content (i) in the address (j), and when the content of the counter 3 is (j), and j'th information on the secondary incoming highway 8 is written in the address (j) of the speech path memory 1, and at the same time, the content of the address (i) of the memory 1 is read out as the j'th speech path information which is transmitted to an external circuit through the secondary outgoing highway 9. Thus, the switching between the i'th speech path and the j'th speech path is performed. Each of the speech paths on the secondary incoming highway 8 corresponds of each of the highways 6-1, 6-2, . . . 6-k, respectively, and each of the speech paths on the secondary outgoing highway 9 corresponds to each of the outgoing highways 7-1, 7-2, . . . 7-k, respectively. Accordingly, since the switching between any speech path on the secondary incoming highway 8 and any speech path on the secondary outgoing speech path 9 can be carried out, the switching between any speech path in the highways 6-1 through 6-k and any outgoing speech path in the highways 7-1 through 7-k can be carried out.
However, the configuration of FIG. 1 has the following disadvantages.
The first desadvantage is that the speech path memory 1 and the holding memory 2 must operate at very high speed. As apparent from the above explanation, the speech path memory 1 is accessed (to write and to read) 2nk times in each time divisional multiplexed frame duration (=125 .mu.S in a typical PCM telephone channel), and the holding memory 2 is accessed nk times in that duration.
The second disadvantage concerns the frame phases of multiplexed highways. The frame phases of all the incoming highways must be the same as one another. And, the frame phases of the outgoing highways are determined by the frame phase of the counter 3, and the frame phase of each highway can not be determined independently. Accordingly, when m number of C-switches (20-1, 20-2, . . . 20-m), and k number of S-switches (Space divisional switch matrix) (21-1, 21-2, . . . 21-K) positioned at the outputs of said C-switches are arranged as shown in FIG. 2 and frame aligners must be installed at all the interface portions of the incoming highways 22-1 through 22-m in order to provide the in-phase situation among the incoming highways. Further, it should be appreciated that the outputs of all the C-switches 23-1, 23-2, 23-3, . . . 23-m are in-phase condition. However, in order to transmit that in-phase condition from the outputs of the C-switches to the inputs of the S-switches, each of the transmission times between the m number of C-switches and k number of S-switches must be the same as one another. Accordingly, the length of the wire, and/or the location of each apparatus is severely restricted.
One solution for solving partially said first disadvantage is shown in the report entitled "Studies on data switch accommodating various data speeds". SE76-46, the Institute of Electronics and Communication Engineers of Japan, September 1976, page 6, in which a speech path memory is divided into k number of sub-memories each relating to the corresponding incoming highway. According to the solution, the number of access times of a memory is reduced to (k+1)/2k times as often as those in the case of FIG. 1, and it should be noted that access times are substantially half of those of FIG. 1 when the value k is large.